The present invention relates to a technology effectively applicable to a cell periphery layout technology or a breakdown voltage enhancing technology in a semiconductor device (or a semiconductor integrated circuit device).
In Japanese Unexamined Patent Publication No. 2007-116190 (Patent Document 1) or, or US Patent No. 2005-098826 (Patent Document 2) corresponding thereto, various structures are disclosed regarding the cell region periphery layout (edge termination structure) of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a super-junction structure manufactured by a multi-epitaxy system or a trench insulation film filling system (trench inside ion implanting system). Examples thereof include a P− resurf region, and a potential fixing electrode with rounded corner parts, and assuming a generally rectangular shape.
Japanese Unexamined Patent Publication No. 2011-108906 (Patent Document 3) mainly discloses a cell region periphery layout (edge termination structure) of a two-dimensional or three-dimensional super-junction type by a trench fill system.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2007-116190    [Patent Document 2]    US Patent No. 2005/098826 A1    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2011-108906